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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
DESCRIPTION
The 87C54/87C58 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C54/87C58 has the same instruction set as the 80C51. This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The 87C58 contains 32k x 8 EPROM memory, and the 87C54 contains 16k x 8 EPROM memory, a volatile 256 x 8 read/write data memory, four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, two-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. For systems that require extra capability, the 87C54/87C58 can be expanded using standard TTL compatible memories and logic. Its added features make it an even more powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multiprocessor communications. See 80C52/54/58 datasheet for ROM device specification.
PIN CONFIGURATIONS
T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 1 2 3 4 5 6 7 8 9 10 DUAL IN-LINE PACKAGE 40 VCC 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA/VPP 30 ALE/PROG 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8
TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15
FEATURES
WR/P3.6 16 RD/P3.7 XTAL2 XTAL1 17 18 19
* 80C51 central processing unit * 16k x 8 EPROM expandable externally to 64k bytes (87C54) * 16k x 8 EPROM (87C54) and
32k x 8 EPROM expandable externally to 64k bytes (87C58) - Improved Quick Pulse programming algorithm - Two level program security system - 32 byte encryption array
VSS 20
SU00748
* 256 x 8 RAM, expandable externally to 64k bytes * Three 16-bit timer/counters
- T2 is an up/down counter
* Four 8-bit I/O ports * Full-duplex enhanced UART
- Framing error detection - Automatic address recognition
* Power control modes
- Idle mode - Power-down mode
* Once (On Circuit Emulation) Mode * Five package styles * OTP package available * Programmable clock out * 6 interrupt sources * 2 level priority
1996 Aug 16
3-215
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
ORDERING INFORMATION
16k x 8 EPROM1 P87C54EBP N P87C54EBF FA P87C54EBA A P87C54EBL KA P87C54EBB B P87C54EFP N P87C54EFF FA P87C54EFA A P87C54EFB B P87C54IBP N P87C54IBF FA P87C54IBA A P87C54IBL KA P87C54IBB B P87C54IFP N P87C54IFF FA P87C54IFA A P87C54IFB B 32k x 8 EPROM1 P87C58EBP N P87C58EBF FA P87C58EBA A P87C58EBL KA P87C58EBB B P87C58EFP N P87C58EFF FA P87C58EFA A P87C58EFB B P87C58IBP N P87C58IBF FA P87C58IBA A P87C58IBL KA P87C58IBB B P87C58IFP N P87C58IFF FA P87C58IFA A P87C58IFB B OTP UV OTP UV OTP OTP UV OTP OTP OTP UV OTP UV OTP OTP UV OTP OTP TEMPERATURE RANGE C AND PACKAGE 0 to +70, 40-Pin Plastic Dual In-line Package 0 to +70, 40-Pin Ceramic Dual In-line Package w/Window 0 to +70, 44-Pin Plastic Leaded Chip Carrier 0 to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window 0 to +70, 44-Pin Plastic Quad Flat Pack -40 to +85, 40-Pin Plastic Dual In-line Package -40 to +85, 40-Pin Ceramic Dual In-line Package w/Window -40 to +85, 44-Pin Plastic Leaded Chip Carrier -40 to +85, 44-Pin Plastic Quad Flat Pack 0 to +70, 40-Pin Plastic Dual In-line Package 0 to +70, 40-Pin Ceramic Dual In-line Package w/Window 0 to +70, 44-Pin Plastic Leaded Chip Carrier 0 to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window 0 to +70, 44-Pin Plastic Quad Flat Pack -40 to +85, 40-Pin Plastic Dual In-line Package -40 to +85, 40-Pin Ceramic Dual In-line Package w/Window -40 to +85, 44-Pin Plastic Leaded Chip Carrier -40 to +85, 44-Pin Plastic Quad Flat Pack FREQUENCY 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 16MHz 24MHz 24MHz 24MHz 24MHz 24MHz 24MHz 24MHz 24MHz 24MHz DRAWING NUMBER SOT129-1 0590B SOT187-2 1472A SOT307-2 SOT129-1 0590B SOT187-2 SOT307-2 SOT129-1 0590B SOT187-2 1472A SOT307-2 SOT129-1 0590B SOT187-2 SOT307-2
NOTE: 1. OTP = One Time Programmable EPROM. UV = Erasable EPROM.
LOGIC SYMBOL
VCC XTAL1 PORT 0 ADDRESS AND DATA BUS VSS
XTAL2 T2 T2EX RST EA PSEN SECONDARY FUNCTIONS ALE RxD TxD INT0 INT1 T0 T1 WR RD PORT 1 PORT 2
PORT 3
ADDRESS BUS
SU00732
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER RAM PORT 0 LATCH
PORT 2 DRIVERS
PORT 2 LATCH
ROM/EPROM
B REGISTER
ACC
STACK POINTER
TMP2
TMP1
PROGRAM ADDRESS REGISTER
ALU
BUFFER
SFRs PSW TIMERS PC INCREMENTER
PROGRAM COUNTER PSEN ALE/PROG EA/VPP RST PD TIMING AND CONTROL INSTRUCTION REGISTER
DPTR
PORT 1 LATCH
PORT 3 LATCH
OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 P1.0-P1.7 PORT 3 DRIVERS
P3.0-P3.7
SU00182
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
Table 1.
SYMBOL ACC* AUXR# B* DPTR: DPH DPL IE* IP*
87C54/87C58 Special Function Registers
DESCRIPTION Accumulator Auxiliary B register Data Pointer (2 bytes) Data Pointer High Data Pointer Low Interrupt Enable Interrupt Priority
DIRECT ADDRESS
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB E7 - F7 E6 - F6 E5 - F5 E4 - F4 E3 - F3 E2 - F2 E1 - F1 E0 AO F0
RESET VALUE 00H xxxxxxx0B 00H
E0H 8EH F0H
83H 82H AF A8H B8H EA BF - 87 AE - BE - 86 AD6 96 - A6 AD14 B6 WR SMOD0 D6 AC AD ET2 BD PT2 85 AD5 95 - A5 AD13 B5 T1 - D5 F0 AC ES BC PS 84 AD4 94 - A4 AD12 B4 T0 POF1 D4 RS1 AB ET1 BB PT1 83 AD3 93 - A3 AD11 B3 INT1 GF1 D3 RS0 AA EX1 BA PX1 82 AD2 92 - A2 AD10 B2 INT0 GF0 D2 OV A9 ET0 B9 PT0 81 AD1 91 T2EX A1 AD9 B1 TxD PD D1 - A8 EX0 B8 PX0 80 AD0 90 T2 A0 AD8 B0 RxD IDL D0 P
00H 00H 00H x0000000B
P0* P1* P2* P3* PCON#
Port 0 Port 1 Port 2 Port 3 Power Control
80H 90H A0H B0H 87H
AD7 97 - A7 AD15 B7 RD SMOD1 D7
FFH FFH FFH FFH 00xxxx00B
PSW* RCAP2H# RCAP2L# SADDR# SADEN# SBUF SCON* SP TCON* T2CON#* TH0 TH1 TH2# TL0 TL1 TL2# TMOD
Program Status Word Timer 2 Capture High Timer 2 Capture Low Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control Timer 2 Control Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 Timer Mode
D0H CBH CAH A9H B9H 99H
CY
00H 00H 00H 00H 00H xxxxxxxxB
9F 98H 81H 8F 88H C8H 8CH 8DH CDH 8AH 8BH CCH C7 89H GATE T2MOD#* Timer 2 Mode Control C9H - * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1. Reset value depends on reset source. TF1 CF TF2 SM0
9E SM1 8E TR1 CE EXF2
9D SM2 8D TF0 CD RCLK
9C REN 8C TR0 CC TCLK
9B TB8 8B IE1 CB EXEN2
9A RB8 8A IT1 CA TR2
99 TI 89 IE0 C9 C/T2
98 RI 88 IT0 C8 CP/RL2 00H 00H 00H 00H 00H 00H 00H 00H 00H 07H
C6 C/T -
C5 M1 -
C4 M0 -
C3 GATE -
C2 C/T -
C1 M1 T2OE
C0 M0 DCEN 00H xxxxxx00B
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
6 1 40
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
44 34
7
39
1
33
LCC 11 17 29
PQFP
23
18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NC* T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 NC* TxD/P3.1 INT0/P3.2 INT1/P3.3 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14
28 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7/A15 PSEN ALE/PROG NC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.5 P1.6 P1.7 RST RxD/P3.0 NC* TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1
12 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG NC* EA/VPP P0.7/AD7
22 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NC* T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4
* DO NOT CONNECT
SU00061
* DO NOT CONNECT
SU00062
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Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
PIN DESCRIPTIONS
PIN NUMBER MNEMONIC VSS VCC P0.0-0.7 DIP 20 40 39-32 LCC 22 44 43-36 QFP 16 38 37-30 TYPE I I I/O NAME AND FUNCTION Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and receives code bytes during EPROM programming. External pull-ups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions include: T2 (P1.0): Timer/Counter 2 external count input/Clockout T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high order address bits during EPROM programming and verification. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. Program Store Enable: The read strobe to external program memory. When the 8XC58 is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 7FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 7FFFH. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. If security bit 1 is programmed, EA will be internally latched on Reset. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
P1.0-P1.7
1-8
2-9
40-44, 1-3
I/O
1 2 P2.0-P2.7 21-28
2 3 24-31
40 41 18-25
I I I/O
P3.0-P3.7
10-17
11, 13-19
5, 7-13
I/O
10 11 12 13 14 15 16 17 RST 9
11 13 14 15 16 17 18 19 10
5 7 8 9 10 11 12 13 4
I O I I I I O O I
ALE/PROG
30
33
27
I/O
PSEN
29
32
26
O
EA/VPP
31
35
29
I
XTAL1
19
21
15
I
XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS - 0.5V, respectively. 1996 Aug 16 3-220
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
TIMER 2
This is a 16-bit up or down counter, which can be operated as either a timer or event counter. It can be operated in one of three different modes (autoreload, capture or as the baud rate generator for the UART). In the autoreload mode the Timer can be set to count up or down by setting or clearing the bit DCEN in the T2CON Special Function Register. The SFR's RCAP2H and RCAP2L are used to reload the Timer upon overflow or a 1-to-0 transition on the T2EX input (P1.1). In the Capture mode Timer 2 can either set TF2 and generate an interrupt or capture its value. To capture Timer 2 in response to a 1-to-0 transition on the T2EX input, the EXEN2 bit in the T2CON must be set. Timer 2 is then captured in SFR's RCAP2H and RCAP2L. As the baud rate generator, Timer 2 is selected by setting TCLK and/or RCLK in T2CON. As the baud rate generator Timer 2 is incremented at 1/2 the oscillator frequency.
idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
Power-Down Mode
To save even more power, a Power Down mode can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated. On the 8XC58 either a hardware reset or external interrupt can use an exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.
POWER OFF FLAG
The Power Off Flag (POF) is set by on-chip circuitry when the VCC level on the 8XC58 rises from 0 to 5V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 3V for the POF to remain unaffected by the VCC level.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
Design Consideration
* When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to two machine cycles before the internal rest algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. The windowed parts must be covered with an opaque label to assure proper chip operation.
*
Reset
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH1 is applied to RESET.
ONCETM Mode
The ONCE ("On-Circuit Emulation") Mode facilitates testing and debugging of systems using the 8XC58 without the 8XC58 having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 8XC58 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Idle Mode
In the idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the
Table 2. External Pin Status During Idle and Power-Down Mode
MODE Idle Idle Power-down Power-down 1996 Aug 16 PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 3-221 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
Programmable Clock-Out
The 87C54/87C58 has a new feature. A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed (1) to input the external clock for Timer/Counter 2 or (2) to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a 16MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: 4 OscillatorFrequency (65536 * RCAP2H, RCAP2L)
address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1101 1100 00X0 1100 0000 1111 1110 1100 000X
Slave 1
In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same.
In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 1110 0000 1111 1010 1110 0X0X 1110 0000 1111 1100 1110 00XX
Enhanced UART
The UART operates in all of the usual modes that are described in the first section of this book for the 80C51. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The 87C54/87C58 UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 1). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 2. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast" address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 3. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are "don't care". The SADEN mask can be logically ANDed with the SADDR to create the "|Given" 1996 Aug 16 3-222
Slave 1
Slave 2
In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary t make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are teated as don't-cares. In most cases, interpreting the don't-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are loaded with 0s. This produces a given address of all "don't cares" as well as a Broadcast address of all "don't cares". this effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register, when set, disables the ALE output. 8XC58 Reduced EMI Mode AUXR (0X8E)
7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 AO
AO: Turns off ALE output.
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
Interrupt Priority Structure
The 87C54/87C58 has a 6-source two-level interrupt structure. There are 3 SFRs associated with the interrupts. They are the IE and IP which are identical in function to those on the 80C51. The priority scheme for servicing the interrupts is the same as that for the 80C51. An interrupt will be serviced as long as an interrupt of
equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed.
Table 3.
Interrupt Table
POLLING PRIORITY 1 2 3 4 5 6 REQUEST BITS IE0 TP0 IE1 TF1 R1, TI TF2, EXF2 HARDWARE CLEAR? N (L) Y (T) Y N (L) Y (T) Y N N VECTOR ADDRESS 03H 0B 13 1B 23 2B X0 T0 X1 T1 SP T2
SOURCE
SCON Address = 98H Bit Addressable SM0/FE Bit: SM1 SM2 5 REN 4 TB8 3 RB8 2 Tl 1 Rl 0
Reset Value = 0000 0000B
7 6 (SMOD0 = 0/1)*
Symbol FE SM0 SM1
Function Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) Serial Port Mode Bit 1 SM0 SM1 Mode 0 0 1 1 0 1 0 1 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate** fOSC/12 variable fOSC/64 or fOSC/32 variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Clear by software to disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
REN TB8 RB8 Tl Rl
NOTE: *SMOD0 is located at PCON6. **fOSC = oscillator frequency
SU00043
Figure 1. SCON: Serial Port Control Register
1996 Aug 16
3-223
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
D0
D1
D2
D3
D4
D5
D6
D7
D8
START BIT
DATA BYTE
ONLY IN MODE 2, 3
STOP BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL
SM0 / FE
SM1
SM2
REN
TB8
RB8
TI
RI
SCON (98H)
SMOD1
SMOD0
OSF
POF
LVF
GF0
GF1
IDL
PCON (87H)
0 : SCON.7 = SM0 1 : SCON.7 = FE
SU00044
Figure 2. UART Framing Error Detection
D0
D1
D2
D3
D4
D5
D6
D7
D8
SM0 1 1
SM1 1 0
SM2 1
REN 1
TB8 X
RB8
TI
RI
SCON (98H)
RECEIVED ADDRESS D0 TO D7 PROGRAMMED ADDRESS COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND "RECEIVED ADDRESS" = "PROGRAMMED ADDRESS" - WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES - WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 3. UART Multiprocessor Communication, Automatic Address Recognition
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING 0 to +70 or -40 to +85 -65 to +150 0 to +13.0 -0.5 to +6.5 15 1.5 UNIT C C V V mA W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 1996 Aug 16 3-224
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
DC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C, VCC = 5V 10%, VSS = 0V TEST SYMBOL VIL VIL1 VIH1 VOL VOL1 VOH VOH1 IIL ITL ILI ICC PARAMETER Input low voltage, except EA Input low voltage to EA Input high voltage, XTAL1, RST Output low voltage, ports 1, 2, 37 Output low voltage, port 0, ALE, PSEN7 Output high voltage, ports 1, 2, 3 3 Output high voltage (port 0 in external bus mode), ALE8, PSEN3 Logical 0 input current, ports 1, 2, 3 Logical 1-to-0 transition current, ports 1, 2, 35 Input leakage current, port 0 Power supply current (See Figure 11): Active mode @ 16MHz Idle mode @ 16MHz Power-down mode Tamb = 0 to +70C Tamb = -40 to +85C Internal reset pull-down resistor Pin capacitance9 (except EA) IOL = 1.6mA2 IOL = 3.2mA2 VCC - 0.7 VCC - 0.7 -50 -650 10 15 3 10 40 32 5 75 100 225 15 IOH = -30A IOH = -3.2mA VIN = 0.4V See note 4 0.45 VIN < VCC - 0.3 See note 10 mA mA A A k pF CONDITIONS MIN -0.5 0 0.7VCC LIMITS TYP1 MAX 0.2VCC-0.1 0.2VCC-0.3 VCC+0.5 0.45 0.45 UNIT V V V V V V V A A A
RRST CIO
NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. This value applies to Tamb = 0C to +70C. For Tamb = -40C to 85C, ITL = -750A. 6. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 7. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA Maximum IOL per port pin: 26mA Maximum IOL per 8-bit port: 71mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 8. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 9. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA it is 25pF). 10. See Figures 12 through 15 for ICC test condition.
1996 Aug 16
3-225
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
AC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V1, 2, 3 16MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX 7 7 7 7 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 750 492 8 0 12tCLCL 10tCLCL-133 2tCLCL-117 0 ns ns ns ns 8 8 8 8 High time Low time Rise time Fall time 20 20 20 20 20 20 tCLCL+tCLCX tCLCL+tCHCX 20 20 ns ns ns ns 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 6 5, 6 5, 6 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high 23 137 122 13 13 287 0 103 tCLCL-40 0 65 350 397 239 3tCLCL-50 4tCLCL-130 tCLCL-50 tCLCL-50 7tCLCL-150 0 tCLCL+40 275 275 147 0 2tCLCL-60 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 4 4 4 4 4 4 4 4 4 4 4 4 PARAMETER Oscillator frequency Speed versions ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 37 207 10 32 142 82 0 tCLCL-25 5tCLCL-105 10 :E 85 22 32 150 tCLCL-30 3tCLCL-45 3tCLCL-105 2tCLCL-40 tCLCL-40 tCLCL-30 4tCLCL-100 ns ns ns ns ns ns ns ns ns ns ns MIN MAX VARIABLE CLOCK MIN 3.5 MAX 16 UNIT MHz
tXHDV 7 Clock rising edge to input data valid 492 10tCLCL-133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 8XC58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.
1996 Aug 16
3-226
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
AC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V1, 2, 3 24MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX 7 7 7 7 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 505 283 3 0 12tCLCL 10tCLCL-133 2tCLCL-80 0 ns ns ns ns 8 8 8 8 High time Low time Rise time Fall time 17 17 5 5 17 17 tCLCL-tCLCX tCLCL-tCHCX 5 5 ns ns ns ns 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 5, 6 6 5, 6 5, 6 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high 17 75 92 12 17 162 0 67 tCLCL-25 0 55 183 210 175 3tCLCL-50 4tCLCL-75 tCLCL-30 tCLCL-25 7tCLCL-130 0 tCLCL+25 150 150 118 0 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-90 ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 4 4 4 4 4 4 4 4 4 4 4 4 PARAMETER Oscillator frequency Speed versions : I ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 17 128 10 17 80 65 0 tCLCL-25 5tCLCL-80 10 43 17 17 102 tCLCL-25 3tCLCL-45 3tCLCL-60 MIN MAX VARIABLE CLOCK4 MIN 3.5 2tCLCL-40 tCLCL-25 tCLCL-25 4tCLCL-65 MAX 24 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
tXHDV 7 Clock rising edge to input data valid 283 10tCLCL-133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 87C58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 24MHz. For frequencies equal or less than 16MHz, see 16MHz "AC Electrial Characteristics", page 3-226.
1996 Aug 16
3-227
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN
tLLAX
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00006
Figure 4. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPF A0-A15 FROM PCH
SU00025
Figure 5. External Data Memory Read Cycle
1996 Aug 16
3-228
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
tQVWX tQVWH
tWHQX
A0-A7 FROM RI OR DPL
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPF
A0-A15 FROM PCH
SU00026
Figure 6. External Data Memory Write Cycle
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1 2 3 4 5 6 7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 7. Shift Register Mode Timing
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 8. External Clock Drive
1996 Aug 16
3-229
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
VCC-0.5
0.2VCC+0.9 VLOAD 0.2VCC-0.1
VLOAD+0.1V VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
0.45V
NOTE: AC inputs during testing are driven at VCC -0.5 for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'.
NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA.
SU00717
SU00718
Figure 9. AC Testing Input/Output
Figure 10. Float Waveform
45 MAX ACTIVE MODE ICCMAX = 1.50 X FREQ. + 8 40
35
30
25 ICC mA 20
TYP ACTIVE MODE 0.9 X FREQ. + 2.5
15
10 MAX IDLE MODE 5 TYP IDLE MODE
4MHz
8MHz
12MHz
16MHz
20MHz
24MHz
FREQ AT XTAL1
SU00046
Figure 11. ICC vs. Frequency
1996 Aug 16
3-230
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
VCC ICC VCC VCC P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS VCC RST P0 EA VCC
VCC ICC
VCC
RST
SU00719
SU00720
Figure 12. ICC Test Condition, Active Mode All other pins are disconnected
Figure 13. ICC Test Condition, Idle Mode All other pins are disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00015
Figure 14. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
VCC ICC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS VCC
SU00016
Figure 15. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 5.5V
1996 Aug 16
3-231
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
EPROM CHARACTERISTICS
The 87C58 is programmed by using a modified Improved Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The 87C58 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C58 manufactured by Philips. Table 4 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 16 and 17. Figure 18 shows the circuit configuration for normal program memory verification.
shown in Figure 18. The other pins are held at the `Verify Code Data' levels indicated in Table 4. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the 32 byte encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 4, and which satisfies the timing specifications, is suitable.
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. For this and secondary effects, it is recommended that an opaque label be placed over the window. For elevated temperature or environments where solvents are being used, apply Kapton tape Fluorglas part number 2345-5, or equivalent. The recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15W-s/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000W/cm2 rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all 1s state.
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in Figure 16. Note that the 87C58 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 16. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 4 are held at the `Program Code Data' levels indicated in Table 4. The ALE/PROG is pulsed low 5 times as shown in Figure 17. To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1FH, using the `Pgm Encryption Table' levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the security bits, repeat the 25 pulse programming sequence using the `Pgm Security Bit' levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot. Program Verification If security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as
Security Bits
With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 (see Table 5) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory, EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled.
Encryption Array
32 bytes of encryption array are initially unprogrammed (all 1s).
TMTrademark phrase of Intel Corporation. 1996 Aug 16 3-232
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
Table 4. EPROM Programming Modes
MODE Read signature Program code data Verify code data Pgm encryption table Pgm security bit 1 Pgm security bit 2 RST 1 1 1 1 1 1 PSEN 0 0 0 0 0 0 ALE/PROG 1 0* 1 0* 0* 0* EA/VPP 1 VPP 1 VPP VPP VPP P2.7 0 1 0 1 1 1 P2.6 0 0 0 0 1 1 P3.7 0 1 1 1 1 0 P3.6 0 1 1 0 1 0 P3.3 0 1 0 1 1 1
NOTES: 1. `0' = Valid low for that pin, `1' = valid high for that pin. 2. VPP = 12.75V 0.25V. 3. VCC = 5V10% during programming and verification. * ALE/PROG receives 5 programming pulses (only for user array; 25 pulses for encryption or security bits) while VPP is held at 12.75V. Each programming pulse is low for 100s (10s) and high for a minimum of 10s.
Table 5. Program Security Bits
PROGRAM LOCK BITS1, 2 SB1 1 2 3 U P P SB2 U U P PROTECTION DESCRIPTION No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. Same as 2, also verify is disabled.
NOTES: 1. P - programmed. U - unprogrammed. 2. Any other combination of the security bits is not defined.
1996 Aug 16
3-233
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
+5V
A0-A7 1 1 1 1
P1 RST P3.6 P3.7 P3.3 XTAL2 87C54 87C58
VCC P0 PGM DATA +12.75V 5 100s PULSES TO GROUND 0 1 0 A8-A13 A14
EA/VPP ALE/PROG PSEN P2.7 P2.6
4-6MHz XTAL1 VSS
P2.0-P2.5 P3.4
SU00183A
Figure 16. Programming Configuration
5 PULSES 1 ALE/PROG: 0
10s MIN 1 ALE/PROG: 0
100s+10
SU00179
Figure 17. PROG Waveform
+5V
VCC A0-A7 1 1 1 0 P1 RST P3.6 P3.7 P3.3 XTAL2 4-6MHz XTAL1 VSS 87C54 87C58 ALE/PROG PSEN P2.7 P2.6 P2.0-P2.5 P3.4 P0 PGM DATA 1 1 0 0 0 A8-A13 A14
EA/VPP
SU00185B
Figure 18. Program Verification
1996 Aug 16
3-234
Philips Semiconductors
Preliminary specification
CMOS single-chip 8-bit microcontrollers
87C54/87C58
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21C to +27C, VCC = 5V10%, VSS = 0V (See Figure 19) SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL NOTE: 1. Not tested. Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 110 48tCLCL 48tCLCL 48tCLCL s s s s PARAMETER MIN 12.5 MAX 13.0 50 1 6 UNIT V mA MHz
PROGRAMMING* P1.0-P1.7 P2.0-P2.5 P3.4 (A0 - A14) ADDRESS
VERIFICATION* ADDRESS
tAVQV
DATA IN DATA OUT
PORT 0 P0.0 - P0.7 (D0 - D7)
tDVGL tAVGL
ALE/PROG
tGHDX tGHAX
tGLGH tSHGL
tGHGL tGHSL
LOGIC 1 EA/VPP LOGIC 0
LOGIC 1
tEHSH
P2.7 ENABLE
tELQV
tEHQZ
SU00180
* FOR PROGRAMMING VERIFICATION SEE FIGURE 16. FOR VERIFICATION CONDITIONS SEE FIGURE 18.
Figure 19. EPROM Programming and Verification
1996 Aug 16
3-235

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